1. Field of the Invention
The present invention relates to photolithography processes. More particularly, the present invention relates to a method for analyzing overlay errors that occur in a lithography process. The method utilizes a new overlay error model to improve the accuracy of overlay error analyses.
2. Description of the Related Art
With decreasing feature sizes and shrinking linewidths of integrated circuits, lithography has become critical for semiconductor manufacture. As the tolerance of linewidth error is increasingly small, lithography machines have been upgraded from step-and-repeat systems (steppers) to advanced step-and-scan systems (scanners). To enhance the resolution and alignment accuracy in lithography, it is necessary to control the overlay errors of lithography to within a tolerance.
Overlay errors are the displacements of present layers relative to the preceding layers, and can be controlled by modifying the equipment setup parameters. For example, US Patent Application Publication No. 2003/0115556 to Conrad et al. discloses a feed-forward method based on correlation of current and prior aligned levels to predict optimum overlay offsets for a given lot.
There have been numerous studies on overlay error modeling and sampling strategies, wherein the overlay errors are generally divided into intrafield overlay errors that occur in one field, i.e., one exposure shot, and interfield overlay errors that occur across the whole wafer. For example, US Patent Application Publication No. 2002/0183989 to Chien et al. discloses an overlay error model and a sampling strategy for steppers. However, most of the existing studies are focused on stepper lithography, while fewer works have addressed overlay error models of the advanced scanner lithography and corresponding sampling strategies. The overlay error models suitable for lithography processes using steppers mostly do not fit for those using scanners.
For lithography processes using scanners, the intrafield overlay errors may come from intrafield translation, isotropic magnification, reticle rotation, asymmetric rotation and asymmetric magnification that are illustrated in FIG. 1, as well as from field skew, scan magnification and scan skew, etc. The interfield overlay errors may come from interfield translation, scale error, wafer rotation and orthogonality error that are illustrated in FIG. 2. Intrafield translation error is caused by translation of the reticle, and isotropic magnification error occurs when the lens moves closer to the reticle or to the wafer. In particular, asymmetric magnification and rotation are caused by the relative movement of the reticle stage and the wafer stage. Interfield translation error is caused by translation of the wafer. Scale error will occur if an absolute movement is given to the stage but results in the stage moving by another amount. Orthogonality error is caused by that the X-Y coordinate system is not parallel to the wafer stage.
However, none of the conventional overlay models fits well enough for lithography processes using scanners. Therefore, the overlay errors occurring in a lithography process using a scanner cannot be analyzed correctly and compensated effectively, so that the accuracy of pattern transfer is difficult to improve.